import chisel3._
import chisel3.util._
class InstrFetchUnit extends Module{
  val io = IO(new Bundle{
    val NewPC = Flipped(DecoupledIO(UInt(32.W)))
    val PC = Output(UInt((32.W)))
    val instr = DecoupledIO(UInt(32.W))

    val instrAddr = Flipped(DecoupledIO(UInt(32.W)))
    val instrData = DecoupledIO(UInt(32.W))
  })
    val PCBase ="hbfc00000".U(32.W)
    io.instrAddr <> io.NewPC
    io.instr <> io.instrData

    io.PC := {
      val PC = RegInit(PCBase)
      when (io.NewPC.fire()){
        PC := io.NewPC
      }
      PC
    }
}
